The invention relates to a semiconductor component having bump-like, metallic lead contacts and multilayer wiring wherein the multilayer wiring is formed of a plurality of conductive tracks with insulating layers therebetween. At a given contact location, various ones of the conductive tracks are commonly connected to a corresponding lead contact.
As is known, electronic semiconductor circuits must be connected to the other parts of an electrical circuit when used, this occurring, for example, by means of solder or wire bonds. Due to the risk of damage, however, this connection is generally not produced directly at the semiconductor component (chip) of such a semiconductor circuit but at a "connecting piece". Such a connecting piece is, for example, a contact dot on the carrier in a so-called micropack construction. This design is well known in the semiconductor industry. It avoids an otherwise necessary direct mechanical access of the component purchaser to the semiconductor component of the semiconductor circuit. The connecting of the contact dot to a corresponding lead contact on the semiconductor component itself, which is still required, is still carried out by the manufacturer of the component in a simultaneous work step for all contact terminals of the component. The procedure is called automatic tape bonding. The contact terminals of the semiconductor component are thus designed as metallic bumps or pillars, and may be formed of a plurality of materials under given conditions, of which at least the uppermost layer is well-solderable or thermocompressible, and either are formed of gold, are coated with a gold layer (contacting ensues via thermocompression), or have at least their surface formed of a solderable material such as gold, silver or copper coated with tin or a lead-tin alloy. They can be situated both at the edge of the semiconductor component, in the so-called inactive region, or can also be situated in the active region thereof.
The increasing complexity and the increasing component density of integrated semiconductor components has led to the fact that the signal and potential management within these components now frequently occurs in so-called multilayer technology in contrast to the earlier single layer technology. The electrical signals and potentials that are employed are thus no longer conducted in only one level but in a plurality of conductive layers respectively separated by electrically insulating layers such as, for example, silicon dioxide, silicon nitride, or various polyimides. The connection of individual layers having identical signals or potentials is thus predominantly provided in the region of the respective lead contact.
Given semiconductor technologies previously standard, as shown in FIG. 1, essentially the following layers then come to lie under an area G of the lead contacts:
1. electric tracks or interconnects 2, 4, 6, and 8 under the entire area G;
2. insulating layers 3, 5, and 7 in such form that they respectively have a large opening under the area G within which parts of the tracks 4, 6, and 8 lie;
3. a so-called final passivation layer 9 on the uppermost track 8, this likewise having a large opening under the area G.
The area G of the lead contacts K is thus defined as the horizontal section plane through a lead contact at that height in which the lead contact has its greatest horizontal expanse on the final passivation layer 9.
In the manufacture of the known semiconductor component, the insulating layers 3, 5, and 7 and the final passivation layer 9 are first applied surface-wide and are then in turn etched off in a sub-region of the area G of the lead contacts K to be applied later, so that cylindrical or cuboid contact holes arise, the contact holes being partially filled with the tracks 4, 6, and 8 of the multilayer wiring formed, for example, of aluminum, aluminum with up to a 4% silicon or a copper constituent, or metal sequences such as titanium, platinum, gold, and/or electrically conductive silicides. Due to the openings in the insulating layers 3, 5, and 7, the tracks 4, 6 and 8 and the insulating layers 3, 5, and 7 thus form steps having a height of more than 3 .mu.m. This can lead to track interruptions U causing reliability and functional problems, and even complete electrical failure.
Applied as the uppermost layer to this arrangement in the region of the area G of the lead contacts K by means of vapor-deposition or sputtering is a 0.1 to 2 .mu.m thin metallic layer sequence as an adhesion layer H and diffusion barrier. It is applied between the track 8 and the final passivation layer 9 and the metallic, bump-like lead contacts K to be provided. The lead contacts K themselves are generated in surface-wide fashion, for example by means of sputtering, or by means of electro-deposition in combination with phototechnique steps. In the case of surface-wide sputtering, they are in turn etched off in those regions outside of the lead contacts K to be produced. Due to the afore-mentioned step heights of greater than 3 .mu.m, and proceeding from the lateral edges of the contact holes, are so-called sputtering gaps S or voids which pass vertically up through the lead contacts K and at which etching agent and electrolyte can then penetrate. This leads to contact causticization, corrosion, and subsequent electrical failure of the semiconductor component.